Conventional techniques related to a test of a semiconductor integrated circuit include the technique described in Japanese Patent Application Laid-Open Publication No. 2003-240822 (Patent Document 1). In the method of Patent Document 1, the duties of the clocks input to scan chains which are respectively formed for clock systems are changed so that the number of flip-flops operated at the same time is reduced, thereby reducing power-supply noise. In the conventional technique described in Patent Document 1, the flip-flops in one clock system are configured to operate at the same time. Therefore, when one clock system is dominant and the majority of flip-flops are driven, power-supply noise cannot be sufficiently reduced.
There is also another conventional technique described in Japanese Patent Application Laid-Open Publication No. 2005-024359 (Patent Document 2). In the method of Patent Document 2, one clock signal source is divided into a plurality of clock signals, and the clock signals of releasing or capturing are shifted with respect to groups of flip-flops which are grouped respectively for supplied clock signals, thereby reducing the power-supply noise. In the conventional technique described in Patent Document 2, the clock system is divided, but since the flip-flops of an entire chip are driven in the releasing or capturing of a scan test, the power-supply noise is not sufficiently reduced.